Networks-on-Chip topology generation techniques: Area and delay evaluation | Ahmed Morgan

Networks-on-Chip topology generation techniques: Area and delay evaluation

Citation:: Morgan, A., H. Elmiligi, W. M. El-Kharashi, F. Gebali, and others, "Networks-on-Chip topology generation techniques: Area and delay evaluation", Design and Test Workshop, 2008. IDT 2008. 3rd International: IEEE, pp. 33–38, 2008.

Abstract:

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