Networks-on-Chip Architecture Customization using Network Partitioning: A System-Level Performance Evaluation | Ahmed Morgan

Networks-on-Chip Architecture Customization using Network Partitioning: A System-Level Performance Evaluation

Citation:: A. A. Morgan, H. Elmiligi, E. - K. G. M. W. F., "Networks-on-Chip Architecture Customization using Network Partitioning: A System-Level Performance Evaluation", International Journal of Computing and Digital Systems, vol. 4, no. 1, pp. 19–31, 2015.

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