Al-Hussein A. El-Shafie, and S. E. D. Habib,
"An all-digital DLL using novel harmonic-free and multi-bit SAR techniques",
Microelectronics Journal, vol. 43: Elsevier, pp. 393-400, 2012.
AbstractA novel Force/Release technique is proposed to eliminate the harmonic locking issue, which occurs in wide-range operation of Delay Locked Loops (DLLs). The proposed technique does not require replica delay line or multiphase clocks for frequency estimation, and hence, reduces the chip area and power consumption. Moreover, it can be employed, without modifications, to any type of the delay line controller. In addition, an area efficient technique for multi-bit Successive Approximation Register (SAR) DLL is proposed. A complete All-Digital DLL (ADDLL) design implementing the proposed Force/Release technique and the proposed 2-bit SAR scheme is developed. All design units are fully digital, described in Verilog and mapped to silicon using the IBM 0.13 μm Artisan standard cell library. The proposed design has an active area of 0.014 mm2 and can operate from 110 MHz to 1 GHz with a fixed latency of one clock cycle. It locks in 12 clock cycles and has a closed loop characteristics.
El-Halym, H. A. A., I. I. Mahmoud, and S. E. D. Habib,
"Proposed hardware architectures of particle filter for object tracking",
EURASIP Journal on Advances in Signal Processing, vol. 2012, no. 1: Springer International Publishing AG, pp. 1–19, 2012.
AbstractIn this article, efficient hardware architectures for particle filter (PF) are presented. We propose three different architectures for Sequential Importance Resampling Filter (SIRF) implementation. The first architecture is a two-step sequential PF machine, where particle sampling, weight, and output calculations are carried out in parallel during the first step followed by sequential resampling in the second step. For the weight computation step, a piecewise linear function is used instead of the classical exponential function. This decreases the complexity of the architecture without degrading the results. The second architecture speeds up the resampling step via a parallel, rather than a serial, architecture. This second architecture targets a balance between hardware resources and the speed of operation. The third architecture implements the SIRF as a distributed PF composed of several processing elements and central unit. All the proposed architectures are captured using VHDL synthesized using Xilinx environment, and verified using the ModelSim simulator. Synthesis results confirmed the resource reduction and speed up advantages of our architectures.
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