Sameh Attia
Research and Teaching Assistant
Electronics and Communications Engineering, Cairo University. (email)
Priority-Select Arbiter: An Efficient Round-Robin Arbiter
- Citation:
- Helal, K., S. Attia, T. Ismail, and H. Mostafa, "Priority-Select Arbiter: An Efficient Round-Robin Arbiter", IEEE International Conference on NEW Circuits and Systems (NEWCAS 2015), Grenoble, France, IEEE, pp. 1-4, 2015.
Abstract:
Round robin arbiter (RRA) is a critical block in nowadays designs. It is widely found in System-on-chips and Network-on-chips. The need of an efficient RRA has increased extensively as it is a limiting performance block. In this paper, we deliver a comparative review between different RRA architectures found in literature. We also propose a novel efficient RRA architecture. The FPGA implementation results of the previous RRA architectures and our proposed one are given, that show the improvements of the proposed RRA.