@conference {7071815,
	title = {A 500 MS/s 6 bits delay line ADC with inherit sample hold},
	booktitle = {Microelectronics (ICM), 2014 26th International Conference on},
	year = {2014},
	note = {n/a},
	month = {Dec},
	pages = {96-99},
	abstract = {n/a},
	keywords = {Analog-digital conversion, analogue-digital conversion, biomedical systems, Clocks, CMOS digital integrated circuits, CMOS integrated circuits, CMOS technology, CMOS Technology Scaling Down, Delay Line, delay line based analog to digital converter, delay lines, Delays, digital signal processing systems, DL-ADC, figure of merit, FOM, frequency 500 MHz, inherit sample \& hold circuits, Inherit sample and hold, power 1.8 mW, power hungry sample and hold circuit, Receivers, sample and hold circuits, size 65 nm, software defined radio receivers, Time-Based ADC, UWB receivers, word length 6 bit},
	doi = {10.1109/ICM.2014.7071815},
	author = {A. H. Hassan and Ali, M. and Mohammed, N. and A Ali and Hassoubh, M. and Ismail, M.W. and Refky, M. and Mostafa, H}
}
