A 4-bit 2ps resolution time-to-digital converter utilizing multi-path delay line for ADPLL | Faisal Hussien, PhD

A 4-bit 2ps resolution time-to-digital converter utilizing multi-path delay line for ADPLL

Citation:: Hassan, O. H., K. R. Rashed, F. A. Hussien, and M. M. Aboudina, "A 4-bit 2ps resolution time-to-digital converter utilizing multi-path delay line for ADPLL", 2019 31st International Conference on Microelectronics (ICM): IEEE, pp. 210–213, 2019.

Abstract:

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Notes:

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