@conference {8686525,
	title = {IDEAL: Image DEnoising AcceLerator},
	booktitle = {2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)},
	year = {2017},
	note = {n/a},
	month = {Oct},
	pages = {82-95},
	abstract = {n/a},
	keywords = {accelerator, approximation theory, Artificial neural networks, block-matching and 3D filtering, CIP, computational imaging, computational imaging pipelines, computerised instrumentation, CPU, DaDianNao, data type precision tuning, Discrete cosine transforms, Energy consumption, general-purpose processor software implementations, GPU, graphics processing units, graphics processor software implementations, Hardware, hardware BM3D accelerator, hardware NN accelerator, IDEAL, image denoising, image denoising accelerator, image filtering, image matching, image sensors, imaging, imaging sensors, matches reuse, microprocessor chips, MR, neural nets, neural network based approximations, neural networks, Noise reduction, off-chip bandwidth consumption, on-chip buffering, optimized software implementations, picture size 8 Mpixel to 42 Mpixel, Software, software-hardware optimization, specialized computing blocks, Three-dimensional displays, UI application, user-interactive applications},
	issn = {1072-4451},
	author = {Mahmoud, M and B. {Zheng} and A. D. {Lascorz} and F. {Heide} and J. {Assouline} and P. {Boucher} and E. {Onzon} and A. {Moshovos}}
}
