A 12-bit, 200MS/s digitally calibrated pipeline ADC with Embedded Sample and Hold | Mohamed Aboudina

A 12-bit, 200MS/s digitally calibrated pipeline ADC with Embedded Sample and Hold

Citation:: Abdelhamid, M. R., K. M. Megawer, F. A. Hussien, and M. M. Aboudina, "A 12-bit, 200MS/s digitally calibrated pipeline ADC with Embedded Sample and Hold", Mediterranean Electrotechnical Conference (MELECON), 2014 17th IEEE: IEEE, pp. 267–280, 2014.

Abstract:

n/a

Notes:

n/a