Mohamed Ahmed Youssef Abdalla

Systems and methods for providing phase shifting in antenna arrays, such as phased antenna arrays of 5G cellular technology, are disclosed. In one aspect, an example phase shift module may include a phase shifter and a frequency multiplier. The phase shifter is configured to receive an LOcal oscillator (LO) signal and output a signal that is phase-shifted by a desired phase shift with respect to the LO signal. The frequency multiplier may be an enhanced frequency multiplier, configured to use not only the phase-shifted signal but also an inverted version of the phase-shifted signal to generate a frequency-multiplied signal having a frequency that is a multiple of the LO signal frequency. In another aspect, an example phase shift module may be configured to apply to an LO signal a phase shift that takes into consideration variations of phase shift over temperature.

This paper describes the design and measurement results of a Gilbert Cell based power detector (PD) for built-in Self-Test (BiST) applications in 5G mm-Wave operating at (24-30 GHz) frequency range. The PD is designed and fabricated in TSMC 0.18um BiCMOS technology. This detector is designed for digitally-assisted calibration for transmitter imperfection such as LO feedthrough and Image Rejection. The proposed differential Gilbert based implementation results in a 58dB common-mode rejection required for LO feedthrough and image rejection calibrations. In the matched frequency range, the simulated input dynamic range is over 48 dB, the detector response is varying by around ±1.25 dB for a given input RF power, as the RF frequency is swept across the operating frequency range. Static power consumption is 16mW from a 3.3 V supply.

This paper presents a linear power amplifier (PA) implemented in 28-nm bulk CMOS process for 5G communication systems with wideband operation in order to cover all possible 5G frequency bands in the United States, Europe, and Asia. The PA is designed using FET stacking technique that allows high output power for low breakdown CMOS devices. The PA has differential inputs and a wideband balun at the output to enable direct interface with single-ended antennas. The wideband balun design will be introduced. The single stage PA shows a measured gain of 10dB, 3 dB bandwidth (BW) from 19 to 43 GHz (77.5%) with 16dBm of maximum output power, 13.6dBm output P1dB at 24 GHz, output IM3 better than 30dBc up to 8dBm output power, and with a peak power added efficiency of 26% with a 2-volt supply.

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This paper describes the design of a Gilbert mixer based channel to channel gain and phase mismatch calibration loop for 5G 4 channels 24:30 GHz beamformers. The input dynamic range of the loop is 14dB centered around the 5G beamformer channel average output power (SdBm) and the simulation results shows that the calibration accuracy is +/-0.25 dB of gain variation and +/-2.5 degrees of phase variations between all channels. The proposed Gilbert cell calibration loop is designed in TSMC 65nm technology with static power consumption of 4 m Watts from 3.3V supply.

This paper describes the design and measurement of a programmable dynamic range square-law power detector (PD) for a wideband mm-Wave transceiver operating at (20-44 GHz) frequency range. The PD is designed and fabricated in TSMC 0.18um BiCMOS technology. Theoretical analysis and CAD harmonic balance simulation were performed to show the detector performance. This detector is designed for Automatic-Gain-control (AGC) for optimizing transceivers performance by setting the received and transmitted power to the required sweet operating spot range. The proposed square-law detector uses programmable resistance to switch between the available detection range, current subtraction technique to increase the available output voltage range, resistor degeneration to reduce the mismatches, and finally input cross capacitors to absorb the conversion gain reduction due to the degeneration and to provide high common mode rejection (CMR). In the matched frequency range, the measured input dynamic range has increased by 7 dB switchable range. The detector response is varying by around ±1 dBV for a given input RF power, as the RF frequency is swept across the operating frequency range. Static power consumption is 5.2mW from a 3.3 V supply.

A Fully integrated 4-element symmetrical TX/RX RF integrated circuit for 26-30 GHz 5G beam-forming system is implemented in 65-nm CMOS technology. Each array element is digitally controlled with 5.625° step and 2 dB gain step. The system employs a heterodyne architecture with 6 GHz intermediate frequency (IF). The up-conversion and down-conversion mixers are integrated on the same chip with a shared LO driver chain. The phased-array power combining/splitting is done using Wilkinson combiner/divider. The RFIC features 3.4 to 3.9 dB noise figure and -5 to -3.5 dBm IIP3 in RX mode, 18 dB maximum power gain and OP1dB of 14.7 dBm per chain in TX mode. The maximum root mean square amplitude and phase error of each array element is 0.25 dB and 1.5°, respectively. The RFIC area is 18 mm2 including pads and it consumes 240 mW per TX chain, 120 mW per RX chain and 174 mW for the LO amplifier with total power of 1.58 W from a 1.2 V supply.

This paper presents the design of a fully integrated CMOS 4-channel phased-array receiver for 10.5-14.5 GHz telecom infrastructure, microwave link and radar applications. The phased-array is built using 0.13μm CMOS, and has a gain of 24.5 dB at 12.5 GHz, an input IIP3 of -7.3 dBm, a NF of 4.8 dB and the RMS phase error is 3o. The chip occupies an area of 2.9×3.2mm with a total power consumption of 204 mW from a 1.5-V supply. This paper presents the design of all the receiver blocks; LNA, phase shifter, combiner and the I/Q mixer, and finally the layout of the full chip and post layout verification and electromagnetic simulations of entire chip are presented. The design and simulations are carried out using different CAD tools like Cadence, ADS and Sonnet.

This paper presents the design of CMOS high linearity I/Q mixer for 9-16-GHz down conversion applications. The mixer is built using 0.13μm CMOS, and it has a gain of 3dB, an input IIP3 of 18dBm, a NF of 15.5 dB, The I/Q mixer achieves a Phase balance of 3°, and amplitude balance of 0.3dB. The mixer occupies an area of 1.5×2.3mm with a total power consumption of 45 mW from a 1.5-V supply, and requires 0dBm LO signal. This paper presents the design and layout of the I/Q mixer and also presents the post layout verification and electromagnetic simulation of the I/Q mixer. The design and simulations are carried out using different CAD tools including Cadence, ADS and sonnet.

A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.

The bandwidth limitation of existing backplanes has become an obstacle to meeting the increasing demand for high-data-rate wireline transmission. In order to compensate for this limitation, TX pre-emphasis, RX continuous-time linear equalizer (CTLE) and DFE are necessary. This work presents a 4-lane transceiver implemented in 40nm CMOS technology that operates over a wide range of data rates from 1 to 12Gb/s (48Gb/s aggregated) using NRZ coding. The supply voltages are 0.9V and 1.8V. An algorithm is developed to adapt the CTLE and DFE to cancel the channel ISI. No inductors are used in the design and ring oscillators are used for both the TX and RX clock generation. This provides a wide frequency-tuning range, small layout area, and high design portability. With extensive use of digital programmability this transceiver is capable of meet ing specifications of different standards, such as PCIe, SATA, and 1 to 10Gb/s Ethernet.

In this paper we present a fully integrated metamaterial-based phase shifter. This design replaces the printed TLs used to obtain the low-pass response with their lumped L-C equivalent circuit. This allows the integration of the phase shifter on single MMIC, and results in a large area saving. Furthermore, the proposed phase shifter achieves a low return loss across the entire tuning range although it does not use any active inductor circuits as in our previous designs. Hence this design is completely passive with no DC power consumption, and is expected to have better linearity and noise performance.

This paper presents a planar electronically steerable series-fed patch array for 2.4-GHz industrial, scientific, and medical band applications. The proposed steerable array uses 0deg tunable positive/negative-refractive-index (PRI/NRI) phase shifters to center its radiation about the broadside direction and allow scanning in both directions off the broadside. Using the PRI/NRI phase shifters also minimizes the squinting of the main beam across the operating bandwidth. The tunable PRI/NRI phase shifters employ 0.13-mum CMOS tunable active inductors, as well as varactors in order to extend their phase tuning range and maintain a low return loss across the entire phase tuning range. The feed network of the proposed array uses lambda/4 impedance transformers. This allows using identical interstage phase shifters, which share the same control voltages to tune all stages. Furthermore, using the impedance transformers in combination with the CMOS-based constant-impedance PRI/NRI phase shifters guarantees a low return loss for the antenna array across its entire scan angle range. The antenna array was fabricated, and is capable of continuously steering its main beam from -27deg to +22deg off the broadside direction with a gain of 8.4 dBi at 2.4 GHz. This is achieved by changing the varactors' control voltage from 3.5 to 15 V. Across the entire scan angle range, the array return loss is less than -10 dB across a bandwidth of 70 MHz, and the relative sidelobe level is always less than -10 dB. Furthermore, the proposed design achieves very low beam squinting of 1.3deg/100 MHz at broadside and a 1-dB compression point of 4.5 dBm.

This paper presents a printed and an integrated bi-directional tunable positive/negative refractive-index phase shifter utilizing CMOS tunable active inductors (TAIs). The printed phase shifter is comprised of a microstrip transmission line (TL), loaded with series varactors and a shunt monolithic microwave integrated circuit (MMIC) synthesizing the TAI. Using the TAI extends the phase tuning range and results in a low return loss across the entire tuning range. The integrated circuit (IC) phase shifter replaces the TLs with suitable lumped L-C sections. This enables integrating the entire phase shifter on a single MMIC, resulting in a compact implementation. The TAI used for both phase shifters is based on a modified gyrator-C architecture, employing a variable resistance to independently control the inductance and quality factor. The TAI is fabricated in the 0.13-mum CMOS process and operates from a 1.5-V supply. The TAI chip is used to implement the TL phase shifter, which achieves a phase of -40deg to +34deg at 2.5 GHz with less than -19-dB return loss from a single stage occupying 10.8 mm times 10.4 mm. The IC phase shifter is fabricated in the same process and achieves a phase from -35deg to +59deg at 2.6 GHz with less than -19-dB return loss from a single stage occupying 550 mum times 1300 mum.

This paper presents an integrated phase shifter based on the high-pass L-C topology. The circuit utilizes both varactors and active inductors to extend the tuning range and achieve a low return loss. The high-pass topology results in a compact IC implementation, and allows phase compensation in series-fed antenna arrays utilizing this phase shifter. Furthermore, this approach allows integrating multiple stages on the same IC, without a significant size increase. A negative resistance is generated by the active inductor circuit, and is used to partially compensate the varactor losses. A test chip is fabricated in a standard 0.13μm CMOS process, and a phase tuning range of 96° is achieved at 4GHz, with a return loss better than -18dB across the entire tuning range. The phase shifter achieves a -2.2dBm input compression point and a 7.4dBm IIP3 while operating from a 1.5V supply.

This paper presents a novel differential 0.13mum CMOS active inductor circuit, which is employed in the design of an integrated negative refractive index metamaterial phase shifter. The active inductor circuit employs a digital/analog tunable feedback resistance to allow controlling both the inductance and the quality factor. The inductance is tunable from 2.5nH to 13.6nH at 5GHz while having a fixed peak quality factor of 100. This results in a phase shift of 36.7deg/stage, at 5GHz, with less than 0.67dB insertion loss

This paper presents a novel tunable metamaterial-based phase-shifter structure utilizing active circuits. It comprises a microstrip transmission line loaded with series varactors and tunable active shunt inductors to increase the phase tuning range and maintain the input & output matching of the metamaterial phase shifter. The proposed phase shifter is capable of providing both a positive and negative phase shift. The active inductors are fabricated in a 0.13mum CMOS process and operate from a 1.5V supply, a 1:2.9 inductance tuning range is measured at 2.5GHz with a tunable peak quality factor >100. The performance of the metamaterial phase shifter unit-cell is simulated using the measured active inductor S-parameters, it achieves a phase tuning range of plusmn20deg at 2.5GHz, with <0.6dB insertion loss and better than -30dB reflection loss

In this paper a new realization of the differential input balanced output current opamp is proposed, operating with ±1.5 V supplies. Its architecture is based on the use of current inverters to sense the input currents while providing a very low input resistance, 23 $Ømega$. The opamp provides a maximum output swing of 700 $μ$A, with an input offset current of 3.5 nA. The differential gain achieved is 65.5 dB, and the differential structure adopted in the design provided a high CMRR, 89.5 dB, the proposed circuit is compared to other realizations with single and differential inputs. The applications of the current opamp are exploited some new applications are presented such as: MOSFET-C integrators, full non-linearity cancellation for MOS transistors, and finally a digitally tuned current-mode variable gain amplifier, which has a gain tuning range of 25 dB with a 0.05 dB step.

This paper presents a new CMOS transconductor providing low distortion for rail-to-rail signals. The circuit is based on using the anti-phase common source topology with the floating current source to extend its linearity range. The difference in the biasing currents of the floating current source is compensated to maintain the two output currents balanced by subtracting it at the output nodes. The proposed transconductor is suitable for applications requiring wide dynamic ranges. Rail-to-rail operation is achieved with THD less than −37 dB. The bandwidth achieved by the transconductor is 67.5 MHz using a supply voltage of ±1.5 V.

This paper describes a graphical method of nonlinear circuit analysis. The method combines circuit analysis using driving-point impedances and signal flow graphs with distortion analysis using the Volterra series. The result is a method of distortion analysis which is more intuitive and flexible than traditional methods. The method is demonstrated in the analysis of a common-emitter amplifier in which the second- and third-order harmonic distortion ratios are determined. The method is also applied to comparing the distortion of different voltage buffer circuits based on an emitter follower and on a differential pair with unity gain feedback

A new CMOS balanced output transconductor is presented. The circuit is based on applying the dynamic biasing technique on the floating current source to extend its linearity range. The difference in the biasing currents is compensated to maintain the two output currents balanced by subtracting it at the output nodes. The proposed transconductor is suitable for high frequency applications requiring a wide dynamic range. Rail-to-rail operation is achieved with THD of −33.64 dB. The bandwidth achieved by the transconductor is 240 MHz, and the supply voltage used is ±1.5 V.

A CMOS fingerprint sensing and parallel processing architecture is implemented on two chips. The first captures the fingerprint and transfers the pattern to the second. The sensors on the first chip are implemented based on a capacitive technique. The parallel processing algorithms include gap removal, spur removal, and thinning. In addition, a novel processing architecture has been implemented using vMOS transistors. Parallel operation of the processing units reduces power dissipation. Both chips use a standard CMOS process, with double poly layers and two metal layers.