Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit

Citation:
A. Wahba, A., and H. A. H. Fahmy, "Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit", {IEEE} {T}ransactions on {C}omputers, vol. 66, no. 2, pp. 226–239, 2017.

Abstract:

In this work we present a new 64-bit floating point Fused Multiply Add (FMA) unit that can perform both binary and decimal addition, multiplication, and fused-multiply-add operations. The presented FMA has 6% less delay than the fastest stand-alone decimal unit and 23% less area than both binary and decimal units together. These results were achieved by the use of: 1) column by column reduction to reduce the partial products in the multiplier tree, 2) a new leading zeros detector that produces its output in base-3 to simplify the normalization shifting in the binary datapath, 3) the use of a redundant adder to perform the final addition, 4) using a new rounding-while-redundant technique to hide the rounding delay and remove it from the critical path, and 5) using a new simple conversion technique from redundant to binary/decimal.

Notes:

DOI: 10.1109/TC.2016.2584067

Related External Link

Tourism