NoC-DPR: A New Simulation Tool Exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) Based FPGA

Citation:
Hassan, A., H. Mostafa, and H. A. H. Fahmy, "NoC-DPR: A New Simulation Tool Exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) Based FPGA", Elsevier Integration VLSI Journal, vol. 63, pp. 204-212, 2018. copy at www.tinyurl.com/y3gy3q2m
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