A Cost-Effective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGA

Citation:
ELdin, A. K., I. Ahmed, A. Obeid, A. Shalash, Y. Ismail, and H. Mostafa, "A Cost-Effective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGA", IEEE International NEW Generation of Circuits and Systems (NGCAS 2017), Genova, Italy, pp. 281-284, 2017. copy at www.tinyurl.com/y4qzomte
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