Publications

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Maximous, G., A. El-Gunidy, H. Mostafa, T. Ismail, and S. Gabran, "A New Sensitivity-Specificity Product-Based Automatic Seizure Detection Algorithm", IEEE International Japan-Africa Conference on Electronics, Communications, and Computers (JAC-ECC ' 2017), Alexandria, Egypt, pp. 115-118, 2017. [PDF]
Maximous, G. S., A. M. Fatahalla, A. Seleym, T. A. Ashour, and H. Mostafa, "A New CAD Tool for Energy Optimization of Diagonal Motion Mode of Attached Electrode Triboelectric Nanogenerators", IEEE International NEW Circuits and Systems Conference (NEWCAS 2018), Montreal, Canada, pp. 331-334, 2018. [PDF]
Mohamed, B. H., A. Taha, A. Shawky, E. Ahmed, A. MohameD, M. Mohsen, R. Samy, A. ELHosiny, A. Ibrahim, and H. Mostafa, "Low Power Design of the Baseband Physical Layer of NarrowBand IoT LTE Uplink Digital Transmitter", Journal of Circuits, Systems, and Computers, In Press.
Mohammed, A., M. Shehata, H. Mostafa, and A. Nassar, "Peak-to-Average Power Ratio Suppression Using Companding Schemes in OFDM Systems", IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, Ontario, Canada, pp. 933-936, 2018. [PDF]
Mohammed, A., M. Shehata, A. Nassar, and H. Mostafa, "Performance Comparison of Companding-Based PAPR Suppression Techniques in OFDM Systems", IEEE International Conference on Modern Circuits and Systems Technology (MOCAST 2019), Thessaloniki, Greece, In Press.
Mohie-Eldin, M., H. A. H. Fahmy, Y. Ismail, N. Gamal, and H. Mostafa, "Leakage Power Evaluation of FinFET-Based FPGA Cluster Under Threshold Voltage Variation", Innternational Design and Test Symposium (IDT 2016), Hammamet, Tunisia ( Best Paper Award: First Place), IEEE, pp. 137-141, 2016. [PDF]
Mohie-Eldin, M., H. Mostafa, H. Fahmy, Y. Ismail, and H. Abdelhamid, "Performance Evaluation of FinFET-Based FPGA Cluster Under Threshold Voltage Variation", IEEE International Conference on NEW Circuits and Systems (NEWCAS 2015), Grenoble, France, IEEE, pp. 1-4, 2015. [PDF]
Mohsen, A., M. Gad, Z. Mahmoud, G. Alshaer, M. Asy, and H. Mostafa, "Remote FPGA Lab for ZYNQ and Virtex-7 Kits", IEEE International Mid-West Symposium on Circuits and Systems (MWSCAS 2019), Dallas, Texas, USA, In Press.
Mostafa, H., M. Anis, and M. Elmasry, "Comparative analysis of process variation impact on flip-flops soft error rate", Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on: IEEE, pp. 103–108, 2009. Abstract[PDF][PPT]

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Mostafa, H., and Y. Ismail, "A Design Oriented Model for Timing Jitter/Skew of Voltage-to-Time Converter (VTC) Circuits", IEEE Canadian Conference on Electrical and Computer Engineering (CCECE'2014), Toronto, Canada, IEEE, pp. 121-126, 2014. [PDF]
Mostafa, H., M. H. Anis, and M. Elmasry, "Analytical soft error models accounting for die-to-die and within-die variations in sub-threshold SRAM cells", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, no. 2: IEEE, pp. 182–195, 2011. Abstract[PDF]

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Mostafa, H., and Y. Ismail, "Modeling the Limitations Imposed by the Timing Jitter/Skew on the Time-Based ADC Performance", IEEE International Conference on Engineering and Technology (ICET'14), Egypt, IEEE, pp. 1-5, 2014. [PDF]
Mostafa, H., M. Anis, and M. Elmasry, "A design-oriented soft error rate variation model accounting for both die-to-die and within-die variations in submicrometer CMOS SRAM cells", Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 57, no. 6: IEEE, pp. 1298–1311, 2010. Abstract[PDF]

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Mostafa, H., and Y. Ismail, "Highly-Linear Voltage-to-Time Converter (VTC) Circuit for Time-Based Analog-to-Digital Converters (T-ADCs)", IEEE International Conference on Electronics, Circuits, and Systems (ICECS'13), Abu Dhabi, United Arab Emirates, IEEE, pp. 149 - 152, 2013. [PDF]
Mostafa, H., M. Anis, and M. Elmasry, "Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells", Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 58, no. 12: IEEE, pp. 2859–2871, 2011. Abstract[PDF]

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Mostafa, H., M. Anis, and M. Elmasry, Robust Design of Variation-Sensitive Digital Circuits, , Waterloo, University of Waterloo, 2011. Abstract[PDF]

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Mostafa, H., M. Anis, and M. Elmasry, "Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits", IEEE Transactions on Very Large Scale Integra- tion Systems (TVLSI), vol. 21, issue 1: IEEE, pp. 92-101, 2013. Abstract[PDF]

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Mostafa, H., and Y. Ismail, "Statistical Yield Improvement Under Process Variations of Multi-Valued Memristor-Based Memories", Elsevier Microelectronics Journal, vol. 51, pp. 46-57, 2016. [PDF]
Mostafa, H., M. Anis, and M. Elmasry, "A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, no. 11: IEEE, pp. 2130–2134, 2011. Abstract[PDF]

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Mostafa, H., M. Anis, and M. Elmasry, "Negative capacitance circuits for process variations compensation and timing yield improvement", IEEE International Conference on Electronics, Circuits, and Systems (ICECS'13) , Abu Dhabi, United Arab Emirates , IEEE, pp. 277 - 280, 2013. [PDF]
Mostafa, H., M. Anis, and M. Elmasry, "A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations Compensation", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, no. 10: IEEE, pp. 1848–1860, 2011. Abstract[PDF]

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Mostafa, H., and Y. Ismail, "Next Generation FPGA", International Conference on Industry Academia Collaboration (IAC'2014), Egypt, pp. 1-4, 2014.
Mostafa, H., and A. M. Soliman, "Novel low-power accurate wide-band cmos negative-second-generation-current-conveyor realizations based on floating-current-source building blocks", Science and Technology for Humanity (TIC-STH), 2009 IEEE Toronto International Conference: IEEE, pp. 720–725, 2009. Abstract[PDF]

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Mostafa, H., M. Anis, and M. Elmasry, "Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops", Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on: IEEE, pp. 1739–1742, 2010. Abstract[PDF][PPT]

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Mostafa, H., and A. M. Soliman, "A modified CMOS realization of the operational transresistance amplifier (OTRA)(vol 60, pg 70, 2006)", FREQUENZ, vol. 60, no. 7-8: FACHVERLAG SCHIELE SCHON MARKGRAFENSTRASSE 11, D-10969 BERLIN, GERMANY, pp. 121–121, 2006. Abstract[PDF]

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Mostafa, H., "Experimental Study of the Adaptive Body Bias on-Chip (ABBoC) for Bias Temperature Instability (BTI) and Process Variations (PV) Compensation", IEEE International Conference on Modern Circuits and Systems Technologies (MOCAST'2018), Thessaloniki, Greece, pp. 1-4, 2018. [PDF]
Mostafa, H., M. Anis, and M. Elmasry, "On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB)", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 20, no. 4: IEEE, pp. 770–774, 2012. Abstract[PDF]

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Mostafa, H., and Y. Ismail, "Process Variation Aware Design of Multi-Valued Spintronic Memristor-Based Memory Arrays", IEEE Transactions on Semiconductor Manufacturing (TSM), vol. 29, issue 2, pp. 145-152, 2016. [PDF]
Mostafa, H., H. Mohamed, and A. M. Soliman, "NOVEL FCS-BASED LAYOUT-FRIENDLY ACCURATE WIDE-BAND LOW-POWER CCII-REALIZATIONS", Journal of Circuits, Systems, and Computers, vol. 19, no. 05: World Scientific, pp. 997–1014, 2010. Abstract[PDF]

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Mostafa, H., and Y. Ismail, "A Design-Oriented Timing Jitter/Skew Model in Voltage-to-Time Converter (VTC) Circuits", Analog Integrated Circuits and Signal Processing, SPRINGER, vol. 82, issue 1, pp. 309-321, 2015. [PDF]
Mostafa, H., M. Anis, and M. Elmasry, "Statistical timing yield improvement of dynamic circuits using negative capacitance technique", Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on: IEEE, pp. 1747–1750, 2010. Abstract[PDF][PPT]

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Mostafa, H., M. Anis, and M. Elmasry, "Negative Capacitance Circuits", IEEE Canadian Conference on Electrical and Computer Engineering (CCECE'2014), Toronto, Canada, IEEE, pp. 127-130, 2014.
Mostafa, H., M. Anis, and M. Elmasry, "Novel timing yield improvement circuits for high-performance low-power wide fan-in dynamic OR gates", Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 58, no. 8: IEEE, pp. 1785–1797, 2011. Abstract[PDF]

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Mostafa, H., M. Anis, and M. Elmasry, Design for Yield and Reliability for Nanometer CMOS Digital Circuits, , Saarbrücken, Germany, LAP LAMBERT Academic Publishing, 2014. COVER.jpgWebsite
Mostafa, H., M. Anis, and M. Elmasry, "Comparative analysis of timing yield improvement under process variations of flip-flops circuits", VLSI, 2009. ISVLSI'09. IEEE Computer Society Annual Symposium on: IEEE, pp. 133–138, 2009. Abstract[PDF][PPT]

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Mostafa, H., and A. M. Soliman, Novel high performance CMOS analog building blocks suitable for analog signal processing, , Cairo, Cairo University, 2005.
Mostafa, H., M. Anis, and M. Elmasry, "The impact of timing yield improvement under process variation on flip-flops soft error rate", Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on: IEEE, pp. 109–117, 2009. Abstract[PDF][PPT]

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Mostafa, H., M. Anis, and M. Elmasry, "NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias", Semiconductor Manufacturing, IEEE Transactions on, vol. 25, no. 3: IEEE, pp. 460–467, 2012. Abstract[PDF]

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