Utilizing Dynamic Partial Reconfiguration to Reduce the Cost of FPGA Debugging | Ahmed Nader Mohieldin, PhD

Utilizing Dynamic Partial Reconfiguration to Reduce the Cost of FPGA Debugging

Citation:: Ahmed, I., A. K. Eldin, H. Mostafa, and A. N. Mohieldin, "Utilizing Dynamic Partial Reconfiguration to Reduce the Cost of FPGA Debugging", IEEE New Circuits and Systems Conference (NEWCAS), Canada, July, 2018.

Date Presented:

July