Area and delay optimization for Networks-on-Chip architectures using Genetic Algorithms

Citation:
Morgan, A., H. Elmiligi, W. M. El-Kharashi, F. Gebali, and others, "Area and delay optimization for Networks-on-Chip architectures using Genetic Algorithms", Design and Test Workshop (IDT), 2009 4th International: IEEE, pp. 1–6, 2009.

Abstract:

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Notes:

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