Hassan, A., A. Ali, M. Ali, M. Hassoubh, N. Mohammed, W. M. Ismail, M. Refky, and H. Mostafa, "A 500 MS/s 6-Bits Delay Line ADC with Inherit Sample & Hold", IEEE International Conference on Microelectronics (ICM), TEXAS A&M, University of QATAR , December 14-17, 2014. Abstract

Analog-to-Digital Converters (ADCs) are essential blocks in digital signal processing systems, software defined radio receivers, and biomedical systems. This paper introduces a 6-bit Delay Line based Analog to Digital Converter (DL-ADC). This DL-ADC utilizes an inherited sample and hold technique to eliminate the dedicated power hungry sample and hold circuit. A prototype of the proposed DL-ADC is implemented in 65nm CMOS technology, where it consumes 1.8 mW and achieves a maximum SNDR of 35.5 dB with sampling rate 500 MHZ with a corresponding Figure of Merit (FOM) of 74.22 fJ/step.

Hussein, A., M. Fawzy, M. W. Ismail, H. Mostafa, and M. Refky, "A 4-Bit 6GS/s Time-Based Analog-To-Digital Converter", EEE International Conference on Microelectron- ics (ICM), TEXAS A&M, University of QATAR , December 14-17, 2014. Abstract

This paper proposes a 4-bit 6GS/s Time-Based Analog-to-Digital Converter (TADC) to be integrated inside the Software Defined Radio (SDR) receivers. The TADC is mainly composed of two blocks which are the Voltage-to-Time Converter (VTC) and the Time-to-Digital Converter (TDC). A prototype of the proposed TADC is implemented using 65 nm technology with a sampling rate of 6GS/s. An ENOB of 3.68 is achieved for an input frequency of 1.331 GHz. The whole system consumes a total power of 21.4 mW.

Data Structure

Semester: 
Spring
class link
Ismail, M. W., and H.Mostafa, "A New Design Methodology for Voltage-to-Time Converters (VTCs) Circuits Suitable for Time-Based Analog-to-Digital Converters (T-ADC)", IEEE INTERNATIONAL SYSTEM-ON-CHIP, Las Vegas, Nevada, USA, 3 September , 2014. Abstract

Voltage-to-Time Converter (VTC) circuit is considered one of the essential blocks in the design of Time-based Analog-to-Digital Converters (T-ADCs). T-ADC is a promising candidate for Software Defined Radio (SDR) receivers that require wide band and high resolution ADC circuits. T-ADC circuits provide higher speed and lower power dissipation compared to conventional ADCs. The proposed design methodology increases the dynamic range of the VTC circuits. Moreover, the adoption of this new methodology results in increasing the VTC circuit sensitivity and improving the VTC linearity. In the proposed case study, the dynamic range increases up to 550mV with maximum linearity error of 3% and sensitivity of 2.13 ps/mV in TSMC 65nm CMOS technology, with a supply voltage of 1.2V.